1. Field of the Invention
The present invention relates to a method for fabricating a non-volatile memory device, and more particularly, the present invention relates to a method for fabricating a non-volatile memory cell having a sidewall gate structure and a siliconoxide-nitride-oxide-silicon (SONOS) cell structure.
A claim of priority is made to Korean Patent Application No. 2002-55002, filed Sep. 11, 2002 in the Korean Intellectual Property Office, which is incorporated herein in its entirety by reference.
2. Description of the Related Art
Semiconductor memory devices used to store data are generally classified as volatile memory devices or non-volatile memory devices. Volatile memory devices lose stored data when the supply of power is stopped, whereas non-volatile memory devices retain stored data even in the absence of power. Accordingly, non-volatile memory devices are widely used when power cannot be continuously supplied or low level power must be used, as in the cases of portable telephone systems, memory cards for storing music and/or image data, and other appliances.
Cell transistors used in non-volatile memory devices typically have a stacked gate structure. The stacked gate structure includes a gate insulating layer, a floating gate electrode, an insulating layer between gates, and a control gate electrode, which are sequentially stacked on a channel region of the cell transistor. In some cases, the non-volatile memory device is formed of a structure which includes a silicon layer having a channel region, an oxide layer forming a tunneling layer, a nitride layer used as a charge trapping layer, an oxide layer used as a blocking layer, and a silicon layer used as a control gate electrode. Such a structure is referred to as a silicon-oxide-nitride-oxide-silicon (SONOS) cell structure.
FIG. 1 is a sectional view illustrating a non-volatile memory device having a conventional SONOS cell structure.
Referring to FIG. 1, an oxide-nitride-oxide (ONO) layer 110 is formed on a silicon substrate 102 having a source region 104 and a drain region 106 which are separated from one another by a given distance. Here, the ONO layer 110 is formed by sequentially stacking a first silicon oxide layer 112 as a tunneling layer, a silicon nitride layer 114 as a charge trapping layer, and a second silicon oxide layer 116 as a blocking layer. A polysilicon layer 120 used as a control gate electrode is formed on the ONO layer 110.
In order to write data in the non-volatile memory device or program the non-volatile memory device, positive bias voltages are applied to the control gate electrode 120 and the drain region 106, and the source region 104 is grounded. The voltages applied to the control gate electrode 120 and the drain region 106 generate vertical and horizontal electric fields along the length of the channel region, which extends from the source region 104 to the drain region 106. The electric fields cause electrons to accelerate from the source region 104 to the drain region 106, and the electrons obtain energy while moving along the length of the channel region. Some of the electrons enter into a “hot” state and travel into the charge trapping layer 114 over the potential barrier of the tunneling layer 112. Since the electrons obtain the largest amount of energy at the channel region in the vicinity of the drain region 106, the possibility of the electrons entering a “hot” state is the largest at the channel region in the vicinity of the drain region 106. When hot electrons enter into the charge trapping layer 114 which is formed of an insulating material, the hot electrons are trapped and stored in the charge trapping layer 114, so the threshold voltage of the memory cell is increased.
In order to erase the non-volatile memory device, voltages are used which are different from the voltages used in programming or reading data from the memory cell. For example, a positive bias voltage is applied to the drain region 106 and a negative bias voltage is applied to the control gate electrode 120. In addition, the source region 104 is floated. Accordingly, the electrons stored in the silicon nitride layer 114 move toward the drain region 106, or holes of the drain region 106 are injected into the silicon nitride layer 114. As a result, the electrons are removed from the silicon nitride layer 114, or the silicon nitride layer 114 is neutralized by the injected holes, so the memory cell is erased.
Recently, a sidewall gate structure has been developed which relies on the phenomenon in which hot electrons are trapped in the portion of the silicon nitride layer 114 around the drain region 106. Here, in the sidewall gate structure, the ONO layer 110 is formed on the portion adjacent to the drain region 106, so the polysilicon layer used as the control gate electrode covers the sidewall of the ONO layer 110.
FIG. 2 is a sectional view illustrating a non-volatile memory device having a sidewall gate structure and a SONOS cell structure. The same reference numerals as those of FIG. 1 denote the same regions or layers, and the descriptions of such elements will not be repeated.
Referring to FIG. 2, an ONO layer 210 is formed by sequentially stacking a first silicon oxide layer 212, a silicon nitride layer 214, and a second silicon oxide layer 214 on a portion of a silicon substrate 102 near a drain region 106. In addition, a third silicon oxide layer 230 is formed as a gate insulating layer on a portion of the silicon substrate 1.02 on which the ONO layer 210 is not formed. A polysilicon layer 220 is formed as a control gate electrode on the ONO layer 210 and the third silicon oxide layer 230. Since the thickness of the ONO layer 210 is larger than the thickness of the third silicon oxide layer 230, the polysilicon layer 220 contacts the portion of the sidewall of the ONO layer 210, and accordingly, the polysilicon layer 220 is referred to as a sidewall gate.
Certain advantages are realized by the non-volatile memory device having a sidewall gate structure and a SONOS cell structure. For example, the electrical characteristics of the device can be improved by adjusting the thickness of the third silicon oxide layer 230. Also, the integration of the device can be improved by forming the ONO layer 210 on the portion of the silicon substrate 102 adjacent to the drain region 106.
However, the fabrication processes of the non-volatile memory device having the sidewall gate structure and the SONOS cell structure must be performed within the limits of photolithography parameters. In particular, a photolithography process is used when forming an etch mask after the ONO layer 210 is stacked. In this case, if the integration degree of the device is substantially increased, a misalignment may occur due to the limits of the photolithography process. As such, there are limits to the degree of integration of the fabricated device.